Iterative stencils are used widely across the spectrum of High Performance Computing (HPC) applications. Many efforts have been put into optimizing stencil GPU kernels, given the prevalence of GPU-accelerated supercomputers. To improve the data locality, temporal blocking is an optimization that combines a batch of time steps to process them together. Under the observation that GPUs are evolving to resemble CPUs in some aspects, we revisit temporal blocking optimizations for GPUs. We explore how temporal blocking schemes can be adapted to the new features in the recent Nvidia GPUs, including large scratchpad memory, hardware prefetching, and device-wide synchronization. We propose a novel temporal blocking method, EBISU, which champions low device occupancy to drive aggressive deep temporal blocking on large tiles that are executed tile-by-tile. We compare EBISU with state-of-the-art temporal blocking libraries: STENCILGEN and AN5D. We also compare with state-of-the-art stencil auto-tuning tools that are equipped with temporal blocking optimizations: ARTEMIS and DRSTENCIL. Over a wide range of stencil benchmarks, EBISU achieves speedups up to $2.53$x and a geometric mean speedup of $1.49$x over the best state-of-the-art performance in each stencil benchmark.

翻译：迭代模板在高性能计算（HPC）应用领域中被广泛使用。鉴于GPU加速超级计算机的普及，人们投入了大量精力来优化模板GPU内核。为了改善数据局部性，时间阻塞是一种将一批时间步合并处理以提升效率的优化技术。基于GPU在若干方面正向CPU演进的观察，我们重新探讨了针对GPU的时间阻塞优化方法。我们研究了如何使时间阻塞方案适配新一代Nvidia GPU的新特性，包括大容量暂存存储器、硬件预取以及设备级同步。我们提出了一种新颖的时间阻塞方法——EBISU，该方法主张通过低设备占用率驱动大尺寸瓦片上的深度时间阻塞，并以瓦片为单位逐块执行。我们将EBISU与当前最先进的时间阻塞库（STENCILGEN和AN5D）进行了比较，同时对比了配备时间阻塞优化的前沿模板自动调优工具（ARTEMIS和DRSTENCIL）。在广泛的模板基准测试中，EBISU相较于各基准中的最佳先进性能实现了最高$2.53$x的加速比，几何平均加速比达$1.49$x。