Lattice-based cryptography (LBC) exploiting Learning with Errors (LWE) problems is a promising candidate for post-quantum cryptography. Number theoretic transform (NTT) is the latency- and energy- dominant process in the computation of LWE problems. This paper presents a compact and efficient in-MEmory NTT accelerator, named MeNTT, which explores optimized computation in and near a 6T SRAM array. Specifically-designed peripherals enable fast and efficient modular operations. Moreover, a novel mapping strategy reduces the data flow between NTT stages into a unique pattern, which greatly simplifies the routing among processing units (i.e., SRAM column in this work), reducing energy and area overheads. The accelerator achieves significant latency and energy reductions over prior arts.

翻译：利用基于 Lattice 的加密法(LBC) 利用学习错误(LWE) 的问题是Qantantum 加密后(LWE) 的很有希望的候选数据。数字理论变换(NTT) 是计算LWE 问题时的惯性与能源主导过程。本文展示了一种紧凑而高效的内装NTT加速器,名为MNTT, 它探索在6T SRAM 阵列内和附近进行优化计算。 具体设计的外围能够快速和高效的模块操作。 此外, 新的绘图战略将NTT阶段之间的数据流减少为一种独特的模式, 从而大大简化了处理单元( 这项工作中的SRAM 列) 之间的路由, 减少了能源和地区管理。 加速器在以前的艺术中实现了显著的惯性与节能减少。