In this paper, we present a new analytical 3D placement framework with a bistratal wirelength model for F2F-bonded 3D ICs with heterogeneous technology nodes based on the electrostatic-based density model. The proposed framework, enabled GPU-acceleration, is capable of efficiently determining node partitioning and locations simultaneously, leveraging the dedicated 3D wirelength model and density model. The experimental results on ICCAD 2022 contest benchmarks demonstrate that our proposed 3D placement framework can achieve up to 6.1% wirelength improvement and 4.1% on average compared to the first-place winner with much fewer vertical interconnections and up to 9.8x runtime speedup. Notably, the proposed framework also outperforms the state-of-the-art 3D analytical placer by up to 3.3% wirelength improvement and 2.1% on average with up to 8.8x acceleration on large cases using GPUs.

翻译：本文提出了一种基于静电密度模型的异构工艺节点面面对接（F2F）键合三维集成电路解析式布局框架，该框架采用双层线长模型。所提框架通过GPU加速，能够利用专用的三维线长模型和密度模型，同时高效确定节点划分与布局位置。在ICCAD 2022竞赛基准测试上的实验结果表明，与一等奖获得者相比，本文提出的三维布局框架可实现最高6.1%（平均4.1%）的线长优化，同时显著减少垂直互连数量并实现最高9.8倍的运行加速。值得注意的是，在大规模算例中，所提框架在GPU支持下比最先进的三维解析布局器实现最高3.3%（平均2.1%）的线长改进，并达到8.8倍的加速效果。