Security validation is an important yet challenging part of the hardware design process, yet, by convention, validation engineers are tasked with defining the threat model, specifying the relevant security properties, detecting any violations of those properties, and assessing the consequences to system security, each of which is manually intensive and may introduce errors. The combined technologies of information flow tracking and specification mining represent an automated approach to property generation and validation, but prior work on information flow tracking on RTL trace data was limited to find cases under which information flowed between registers, without reproducing full paths to capture how sensitive information propagates through a design. With the introduction of new technologies accelerating hardware analysis, we develop a novel approach for constructing information flow paths from register transfer level (RTL) trace data.

翻译：安全验证是硬件设计过程中重要且具有挑战性的环节，然而按照惯例，验证工程师需要负责定义威胁模型、指定相关安全属性、检测这些属性的任何违规行为，并评估对系统安全的影响——每个环节均需要大量人工操作且可能引入错误。信息流追踪与规约挖掘相结合的自动化技术，为代表属性生成与验证的自动化方法提供了可能。但先前基于RTL迹线数据的信息流追踪研究仅局限于发现寄存器间信息流动的案例，未能重构完整路径以揭示敏感信息在设计中的传播过程。随着加速硬件分析的新技术引入，我们提出了一种从寄存器传输级(RTL)迹线数据构建信息流路径的新颖方法。