Battery-less technology evolved to replace battery technology. Non-volatile memory (NVM) based processors were explored to store the program state during a power failure. The energy stored in a capacitor is used for a backup during a power failure. Since the size of a capacitor is fixed and limited, the available energy in a capacitor is also limited and fixed. Thus, the capacitor energy is insufficient to store the entire program state during frequent power failures. This paper proposes an architecture that assures safe backup of volatile contents during a power failure under energy constraints. Using a proposed dirty block table (DBT) and writeback queue (WBQ), this work limits the number of dirty blocks in the L1 cache at any given time. We further conducted a set of experiments by varying the parameter sizes to help the user make appropriate design decisions concerning their energy requirements. The proposed architecture decreases energy consumption by 17.56%, the number of writes to NVM by 18.97% at LLC, and 10.66% at a main-memory level compared to baseline architecture.

翻译：无电池技术逐步取代电池技术。基于非易失性存储器（NVM）的处理器被开发用于在断电时保存程序状态。电容器中存储的能量用于断电期间的备份。由于电容器容量固定且有限，其可用能量同样有限且固定。因此，在频繁断电时，电容器能量不足以完整保存程序状态。本文提出一种在能量约束下确保掉电时易失性内容安全备份的架构。通过采用所提出的脏块表（DBT）和写回队列（WBQ），本工作限制了L1缓存中任意时刻的脏块数量。我们进一步通过改变参数规模开展了一系列实验，以帮助用户根据自身能量需求做出合理的设计决策。与基准架构相比，所提架构将能耗降低17.56%，LLC层NVM写入次数减少18.97%，主存层NVM写入次数减少10.66%。