The rapid growth of deep neural networks (DNNs) has exposed fundamental limitations in electronic accelerators, where data movement dominates energy consumption, commonly referred to as the memory wall. Photonic accelerators offer a compelling alternative due to their inherent parallelism and high-speed matrix operations. However, existing research largely focuses on device-level innovations, leaving system-level scalability insufficiently explored. In this paper, we present a scalable photonic accelerator architecture based on a modular scale-out paradigm using 4 X 4 photonic tensor core units. We perform a systematic architectural analysis that incorporates the practical scaling limits of photonic hardware, including insertion loss, fanout penalties, and laser power limits, which restrict monolithic photonic scaling. Through evaluation on representative DNN workloads (GoogleNet, ResNet-18, MobileNet, and AlphaGo Zero) with up to 1024 processing elements, we identify a topology-dominated scaling bottleneck in the photonic domain, termed the Utilization Wall, where performance is governed by grid topology rather than hardware size. We further establish the Symmetric Grid Rule, demonstrating that symmetric topologies improve utilization by up to 6X while reducing memory access by over 40% compared to linear configurations, which reveal that topology-aware scaling is essential for achieving energy-efficient and high-performance photonic AI accelerators.

翻译：深度神经网络（DNN）的快速发展暴露了电子加速器中的根本性局限，其中数据传输主导能耗，这通常被称为“存储墙”。光子加速器凭借其固有的并行性和高速矩阵运算能力，提供了一种引人注目的替代方案。然而，现有研究主要集中于器件层面的创新，系统级可扩展性仍未得到充分探索。本文提出了一种基于模块化横向扩展范式的可扩展光子加速器架构，该架构采用4×4光子张量核心单元。我们进行了系统级的架构分析，纳入了光子硬件的实际扩展限制，包括插入损耗、扇出代价和激光功率限制，这些因素制约了单片光子扩展。通过对代表性DNN工作负载（GoogleNet、ResNet-18、MobileNet和AlphaGo Zero）进行评估（最多使用1024个处理单元），我们识别出光子领域中的拓扑主导扩展瓶颈，称为“利用率墙”，其性能取决于网格拓扑而非硬件规模。我们进一步建立了对称网格规则，证明与线性配置相比，对称拓扑可将利用率提升高达6倍，同时减少超过40%的内存访问。这表明拓扑感知扩展对于实现高能效和高性能的光子AI加速器至关重要。