This paper presents an automated approach for designing processors that support a subset of the RISC-V instruction set architecture (ISA) for a new class of applications at Extreme Edge. The electronics used in extreme edge applications must be area and power-efficient, but also provide additional qualities, such as low cost, conformability, comfort and sustainability. Flexible electronics, rather than silicon-based electronics, will be able to meet the above qualities. For this purpose, we propose a methodology for generating RISC-V instruction subset processors (RISSPs) tailored to these applications and implementing them as flexible integrated circuits (FlexICs). The methodology makes verification an integral part of the processor design by treating each instruction in the ISA as a discrete, fully functional, pre-verified hardware block. It automatically builds a custom processor by stitching together the instruction hardware blocks required by an application or a set of applications in a specific domain. We generate RISSPs using the proposed methodology for three extreme edge applications, and embedded applications from the Embench benchmark suite. When synthesized, RISSPs can achieve 8-to-43% reduction in area and 3-to-30% reduction in power compared to a processor supporting the full RISC-V ISA, and are also on average ~40 times more energy efficient than Serv - the world's smallest 32-bit RISC-V processor. When physically implemented as FlexICs, the three extreme edge RISSPs achieve up to 42% area and 21% power savings with respect to the full RISC-V processor.

翻译：本文提出了一种自动化方法，用于设计支持RISC-V指令集架构（ISA）子集的处理器，以面向极致边缘应用的新类别。极致边缘应用中的电子器件必须具有面积和功耗效率，同时还需具备低成本、可适应性、舒适性和可持续性等附加特性。相较于硅基电子器件，柔性电子器件将能够满足上述要求。为此，我们提出了一种方法，用于生成针对这些应用定制的RISC-V指令子集处理器（RISSPs），并将其实现为柔性集成电路（FlexICs）。该方法将验证作为处理器设计的核心部分，将ISA中的每条指令视为离散、功能完整且预先验证的硬件模块。通过自动拼接特定领域应用或应用集合所需的指令硬件模块，构建定制处理器。我们使用所提出的方法为三个极致边缘应用以及Embench基准测试套件中的嵌入式应用生成了RISSPs。综合结果显示，与支持完整RISC-V ISA的处理器相比，RISSPs在面积上可减少8%至43%，功耗降低3%至30%，且平均能效比Serv（世界上最小的32位RISC-V处理器）高出约40倍。当作为FlexICs物理实现时，三个极致边缘RISSPs相较于完整RISC-V处理器，面积最多可节省42%，功耗降低21%。