In a context of ever-growing worldwide communication traffic, cloud service providers aim at deploying scalable infrastructures to address heterogeneous needs. Part of the network infrastructure, FPGAs are tailored to guarantee low-latency and high-throughput packet processing. However, slowness of the hardware design process impairs FPGA ability to be part of an agile infrastructure under constant evolution, from incident response to long-term transformation. Deploying and maintaining network functionalities across a wide variety of FPGAs raises the need to fine-tune hardware designs for several FPGA targets. To address this issue, we introduce PAF, an open-source architectural parameterization framework based on a pipeline-oriented design methodology. PAF (Pipeline Automation Framework) implementation is based on Chisel, a Scala-embedded Hardware Construction Language (HCL), that we leverage to interface with circuit elaboration. Applied to industrial network packet classification systems, PAF demonstrates efficient parameterization abilities, enabling to reuse and optimize the same pipelined design on several FPGAs. In addition, PAF focuses the pipeline description on the architectural intent, incidentally reducing the number of lines of code to express complex functionalities. Finally, PAF confirms that automation does not imply any loss of tight control on the architecture by achieving on par performance and resource usage with equivalent exhaustively described implementations.

翻译：在全球通信流量持续增长的背景下，云服务提供商致力于部署可扩展的基础设施以满足异构需求。作为网络基础设施的组成部分，FPGA因其能够保证低延迟与高吞吐量的数据包处理能力而备受青睐。然而，硬件设计流程的缓慢阻碍了FPGA成为敏捷且持续演进基础设施（从事件响应到长期转型）的一部分。在多种FPGA平台上部署和维护网络功能，需要对不同FPGA目标进行硬件设计的精细调优。为解决这一问题，我们提出了PAF——一个基于流水线导向设计方法的开源架构参数化框架。PAF（Pipeline Automation Framework）的实现基于Chisel（一种嵌入Scala的硬件构造语言），我们利用该语言实现与电路细化的接口。将PAF应用于工业网络数据包分类系统时，其展示了高效的参数化能力，能够在多种FPGA上复用和优化相同的流水线设计。此外，PAF将流水线描述聚焦于架构意图，从而显著减少了表达复杂功能所需的代码行数。最后，通过与同等详尽描述的实现方案在性能与资源使用上达到同等水平，PAF证实了自动化并不会导致对架构严密控制力的丧失。