Memory management is necessary with the increasing number of multi-connected AI devices and data bandwidth issues. For this purpose, high-speed multi-port memory is used. The traditional multi-port memory solutions are hard-bounded to a fixed number of ports for read or write operations. In this work, we proposed a pseudo-quad-port memory architecture. Here, ports can be configured (1-port, 2-port, 3-port, 4-port) for all possible combinations of read/write operations for the 6T static random access memory (SRAM) memory array, which improves the speed and reduces the bandwidth for data transfer. The proposed architecture improves the bandwidth of data transfer by 4x. The proposed solution provides 1.3x and 2x area efficiency as compared to dual-port 8T and quad-port 12T SRAM. All the design and performance analyses are done using 65nm CMOS technology.

翻译：随着多连接AI设备数量的增加和数据带宽问题的凸显，存储器管理变得至关重要。为此，需要采用高速多端口存储器。传统的多端口存储器解决方案在读写操作端口数量上通常固定不变。本研究提出了一种伪四端口存储器架构。该架构基于6T静态随机存取存储器（SRAM）阵列，其端口可配置为（1端口、2端口、3端口、4端口）以适应所有可能的读写操作组合，从而提升数据传输速度并降低带宽需求。所提架构使数据传输带宽提升至4倍。与双端口8T和四端口12T SRAM相比，该方案分别实现了1.3倍和2倍的面积效率提升。所有设计与性能分析均基于65纳米CMOS工艺完成。