Weak memory models allow for simplified hardware and increased performance in the memory hierarchy at the cost of increased software complexity. In weak memory models, explicit synchronization is needed to enforce ordering between different processors. Acquire and release semantics provide a powerful primitive for expressing only the ordering required for correctness. In this project, we explore adding load-acquire and store-release instructions to the RISC-V ISA. We add support to the herd formal memory model, the gem5 cycle-approximate simulator, and the LLVM/Clang toolchain. Because these instructions do not exist in the RISC-V standard, there is an inherent urgency to ratify explicit load-acquire/store-release instructions in order to prevent multiple ABI implementations and ecosystem fragmentation. We found that for workloads with a high degree of sharing and heavy contention, the impact of less memory ordering is muted, but our changes successfully encode the semantics we desire.

翻译：弱内存模型通过降低内存层次结构中的硬件复杂度并提升性能，但增加了软件复杂性。在弱内存模型中，需要通过显式同步来强制不同处理器之间的顺序性。获取与释放语义提供了一种强大的原语，仅需表达正确性所需的排序约束。本项目探索了向RISC-V ISA添加加载-获取（load-acquire）与存储-释放（store-release）指令。我们为herd形式化内存模型、gem5周期近似模拟器以及LLVM/Clang工具链添加了相应支持。由于这些指令尚未纳入RISC-V标准，为防止出现多种ABI实现及生态系统碎片化，亟需尽快批准显式加载-获取/存储-释放指令。实验表明，对于具有高共享度与强竞争的工作负载，减少内存排序的影响较小，但我们的修改成功编码了所需的语义。