The integration of Large Language Models (LLMs) into Electronic Design Automation (EDA) and hardware security is rapidly reshaping the semiconductor industry. While LLMs offer unprecedented capabilities in generating Register Transfer Level (RTL) code, automating testbenches, and bridging the semantic gap between high-level specifications and silicon, they simultaneously introduce severe vulnerabilities. This comprehensive review provides an in-depth analysis of the state-of-the-art in LLM-driven hardware design, organized around key advancements in EDA synthesis, hardware trust, design for security, and education. We systematically expand on the methodologies of recent breakthroughs -- from reasoning-driven synthesis and multi-agent vulnerability extraction to data contamination and adversarial machine learning (ML) evasion. We integrate general discussions on critical countermeasures, such as dynamic benchmarking to combat data memorization and aggressive red-teaming for robust security assessment. Finally, we synthesize cross-cutting lessons learned to guide future research toward secure, trustworthy, and autonomous design ecosystems.

翻译：大型语言模型（LLM）与电子设计自动化（EDA）及硬件安全的融合正在重塑半导体行业。尽管LLM在生成寄存器传输级（RTL）代码、自动化测试平台以及弥合高层规范与硅芯片之间的语义鸿沟方面展现出前所未有的能力，但它们同时也引入了严重的安全漏洞。本综述全面深入分析了LLM驱动的硬件设计领域最新研究进展，围绕EDA综合、硬件可信性、安全设计及教育等关键方向展开论述。我们系统性地阐述了近期突破性方法——从推理驱动综合、多智能体漏洞提取到数据污染与对抗性机器学习（ML）规避技术。针对关键对抗措施（如对抗数据记忆的动态基准测试以及用于鲁棒安全评估的激进红队演练）进行了综合讨论。最后，我们凝练出跨学科经验教训，以引导未来研究走向安全、可信且自主的设计生态系统。