The integration of Large Language Models (LLMs) into Electronic Design Automation (EDA) and hardware security is rapidly reshaping the semiconductor industry. While LLMs offer unprecedented capabilities in generating Register Transfer Level (RTL) code, automating testbenches, and bridging the semantic gap between high-level specifications and silicon, they simultaneously introduce severe vulnerabilities. This comprehensive review provides an in-depth analysis of the state-of-the-art in LLM-driven hardware design, organized around key advancements in EDA synthesis, hardware trust, design for security, and education. We systematically expand on the methodologies of recent breakthroughs -- from reasoning-driven synthesis and multi-agent vulnerability extraction to data contamination and adversarial machine learning (ML) evasion. We integrate general discussions on critical countermeasures, such as dynamic benchmarking to combat data memorization and aggressive red-teaming for robust security assessment. Finally, we synthesize cross-cutting lessons learned to guide future research toward secure, trustworthy, and autonomous design ecosystems.

翻译：大语言模型与电子设计自动化及硬件安全的融合正在迅速重塑半导体产业。尽管大语言模型在生成寄存器传输级代码、自动化测试平台以及弥合高层规范与芯片实现之间的语义鸿沟方面展现出前所未有的能力，但同时也引入了严重的安全脆弱性。本综述对基于大语言模型的硬件设计前沿技术进行了深入分析，围绕电子设计自动化综合、硬件可信性、安全设计及教育等关键进展展开论述。我们系统阐述了近期突破性方法——从推理驱动综合与多智能体漏洞提取，到数据污染与对抗性机器学习逃逸。本文整合了关键防御措施的综合讨论，例如通过动态基准测试对抗数据记忆化，以及通过激进的红队测试实现稳健安全评估。最后，我们提炼了跨领域经验教训，以引导未来研究迈向安全、可信且自主的设计生态系统。