The integration of Large Language Models (LLMs) into Electronic Design Automation (EDA) and hardware security is rapidly reshaping the semiconductor industry. While LLMs offer unprecedented capabilities in generating Register Transfer Level (RTL) code, automating testbenches, and bridging the semantic gap between high-level specifications and silicon, they simultaneously introduce severe vulnerabilities. This comprehensive review provides an in-depth analysis of the state-of-the-art in LLM-driven hardware design, organized around key advancements in EDA synthesis, hardware trust, design for security, and education. We systematically expand on the methodologies of recent breakthroughs -- from reasoning-driven synthesis and multi-agent vulnerability extraction to data contamination and adversarial machine learning (ML) evasion. We integrate general discussions on critical countermeasures, such as dynamic benchmarking to combat data memorization and aggressive red-teaming for robust security assessment. Finally, we synthesize cross-cutting lessons learned to guide future research toward secure, trustworthy, and autonomous design ecosystems.

翻译：大语言模型（LLMs）向电子设计自动化（EDA）和硬件安全领域的融合正迅速重塑半导体行业。尽管LLMs在生成寄存器传输级（RTL）代码、自动化测试平台以及弥合高层级规范与芯片实现之间的语义鸿沟方面展现出前所未有的能力，但同时也引入了严重的脆弱性。本综述对LLM驱动的硬件设计前沿技术进行了深度解析，围绕EDA综合、硬件可信性、安全设计及教育等关键突破领域展开系统梳理。我们系统性地阐述了近期突破性方法论——从基于推理的综合与多智能体漏洞提取，到数据污染与对抗性机器学习（ML）规避。通过整合关键对抗措施（如对抗数据记忆化的动态基准测试与强化安全评估的激进红队测试）的普适性讨论，最终提炼出跨领域经验教训，以引导未来研究走向安全可信且自主化的设计生态系统。