Sorting is a fundamental operation across numerous computational domains. Traditionally, this process involves transferring data from main memory to a processing unit for sorting, followed by writing the sorted data back to memory. This conventional approach incurs substantial latency and energy overheads due to the extensive data movement between memory and processing components. To mitigate these overheads, this paper introduces novel architectures for executing sorting operations directly within the memory fabric, eliminating the need for off-chip data transfer. To our knowledge, this work represents the first exploration of in-memory sorting using 6T SRAM. The proposed architecture is designed to operate on data represented in the standard weighted binary radix format commonly used in digital systems. The proposed architecture achieves a significant 3.4x reduction in latency compared to memristor-based IMC sorting.

翻译：排序是众多计算领域中的一项基础操作。传统上，该过程涉及将数据从主存传输到处理单元进行排序，然后将排序后的数据写回内存。这种传统方法由于内存与处理组件之间的大量数据移动，会带来显著的延迟和能耗开销。为缓解这些开销，本文提出了一种新型架构，可直接在内存结构内部执行排序操作，从而消除片外数据传输的需求。据我们所知，本工作是首次探索使用6T SRAM进行内存排序。所提出的架构设计用于处理数字系统中常用的标准加权二进制基数格式表示的数据。与基于忆阻器的IMC排序相比，所提出的架构实现了显著的3.4倍延迟降低。