Compute-in-memory (PIM) mitigates the memory wall by performing computation within memory, reducing data movement and improving energy efficiency. DRAM-based PIM is particularly attractive due to its high density, mature manufacturing ecosystem, and compatibility with existing systems. Recent works exploit multiple levels of the DRAM hierarchy - including subarrays, banks, and 3D-stacked organizations - to enable in-memory computation using mechanisms such as multi-row activation, row-buffer operations, and near-bank compute units. However, these approaches introduce non-traditional current demand patterns that challenge the power delivery network (PDN). This paper surveys PDN challenges in DRAM-based PIM systems and proposes a unified taxonomy that characterizes PIM-induced current behavior along temporal (burst vs. sustained) and spatial (localized vs. distributed) dimensions. Using this framework, we analyze how representative PIM techniques stress the PDN through bursty activations, multi-row concurrency, and large-scale parallel execution, leading to voltage droop, IR drop, and thermal hotspots. We further discuss DRAM-specific mitigation strategies leveraging existing architectural and circuit-level mechanisms, including timing constraints, memory controller scheduling, data placement, and bank- and vault-level power management. This survey highlights the importance of PDN-aware design for scalable and reliable DRAM-based PIM systems and outlines key future research directions.

翻译：存内计算通过在存储器内部执行计算，减少数据搬运并提升能效，从而缓解存储墙问题。基于DRAM的存内计算因其高密度、成熟的制造生态系统以及与现有系统的兼容性而具有特殊吸引力。近期研究利用DRAM层次结构的多个层面——包括子阵列、存储体和3D堆叠结构——通过行激活、行缓冲操作和近存储体计算单元等机制实现内存计算。然而，这些方法引入了非传统的电流需求模式，给供电网络带来挑战。本文综述了基于DRAM的存内计算系统中的供电网络挑战，并提出了一个统一的分类体系，该体系从时间维度（瞬发式与持续式）和空间维度（局部化与分布式）描述存内计算引发的电流行为。利用该框架，我们分析了典型存内计算技术如何通过突发行激活、多行并发和大规模并行执行对供电网络造成压力，从而导致电压跌落、IR压降和热热点。我们进一步讨论了利用现有架构和电路级机制（包括时序约束、内存控制器调度、数据放置以及存储体和存储层级的电源管理）的DRAM特有缓解策略。本综述强调了感知供电网络的设计对于可扩展且可靠的基于DRAM的存内计算系统的重要性，并指出了关键的未来研究方向。