Power and cost constraints in the internet-of-things (IoT) extreme-edge and TinyML domains, coupled with increasing performance requirements, motivate a trend toward heterogeneous architectures. These designs use energy-efficient application-class host processors to coordinate compute-specialized multicore accelerators, amortizing the architectural costs of operating system support and external communication. This brief presents Cheshire, a lightweight and modular 64-bit Linux-capable host platform designed for the seamless plug-in of domain-specific accelerators. It features a unique low-pin-count DRAM interface, a last-level cache configurable as scratchpad memory, and a DMA engine enabling efficient data movement to or from accelerators or DRAM. It also provides numerous optional IO peripherals including UART, SPI, I2C, VGA, and GPIOs. Cheshire's synthesizable RTL description, comprising all of its peripherals and its fully digital DRAM interface, is available free and open-source. We implemented and fabricated Cheshire as a silicon demonstrator called Neo in TSMC's 65nm CMOS technology. At 1.2 V, Neo achieves clock frequencies of up to 325 MHz while not exceeding 300 mW in total power on data-intensive computational workloads. Its RPC DRAM interface consumes only 250 pJ/B and incurs only 3.5 kGE in area for its PHY while attaining a peak transfer rate of 750 MB/s at 200 MHz.

翻译：摘要：物联网（IoT）极边缘与TinyML领域中的功耗与成本限制，加之日益增长的性能需求，推动着异构架构的发展趋势。此类设计采用能效优化的应用级主控处理器，协调计算专用的多核加速器，从而分摊操作系统支持与外部通信的架构开销。本文介绍Cheshire——一款支持Linux的轻量级模块化64位主控平台，专为无缝集成领域专用加速器而设计。该平台具备独特的低引脚数DRAM接口、可配置为便签存储器的末级缓存，以及支持加速器或DRAM间高效数据搬移的DMA引擎。此外，它还提供包括UART、SPI、I2C、VGA与GPIO在内的多种可选IO外设。Cheshire的可综合RTL描述（包含所有外设及全数字DRAM接口）已免费开源发布。我们基于台积电65nm CMOS工艺实现了Cheshire的硅演示芯片Neo并完成流片。在1.2V电压下，Neo在数据密集型计算负载中可达到325MHz时钟频率，且总功耗不超过300mW。其RPC DRAM接口功耗仅250 pJ/B，物理层面积仅3.5 kGE，同时在200MHz频率下可实现750MB/s的峰值传输速率。