Multi-die FPGAs are widely adopted to deploy large hardware accelerators. Two factors impede the performance optimization of HLS designs implemented on multi-die FPGAs. On the one hand, the long net delay due to nets crossing die-boundaries results in an NP-hard problem to properly floorplan and pipeline an application. On the other hand, traditional automated searching flow for HLS directive optimizations targets single-die FPGAs, and hence, it cannot consider the resource constraints on each die and the timing issue incurred by the die-crossings. Further, it leads to an excessively long runtime to legalize the floorplan of HLS designs generated under each group of configurations during directive optimization due to the large design scale. To co-optimize the directives and floorplan of HLS designs on multi-die FPGAs, we propose the FADO framework, which formulates the directive-floorplan co-search problem based on the multi-choice multi-dimensional bin-packing and solves it using an iterative optimization flow. For each step of directive search, a latency-bottleneck-guided greedy algorithm searches for more efficient directive configurations. For floorplanning, instead of repetitively incurring global floorplanning algorithms, we implement a more efficient incremental floorplan legalization algorithm. It mainly applies the worst-fit online bin-packing algorithm to balance the floorplan, together with an offline best-fit-decreasing re-packing to compact the floorplan, followed by pipelining of long wires crossing die-boundaries. Through experiments on HLS designs mixing dataflow and non-dataflow kernels, FADO not only well-automates the co-optimization and finishes within 693X~4925X shorter runtime, compared with DSE assisted by global floorplanning, but also yields an improvement of 1.16X~8.78X in overall workflow execution time after implementation on the Xilinx Alveo U250 FPGA.

翻译：摘要：多晶粒FPGA被广泛用于部署大规模硬件加速器。两个因素阻碍了在多层FPGA上实现的高层次综合（HLS）设计的性能优化。一方面，由于跨越晶粒边界的互连导致的长线延迟，使得应用电路进行合理布局布线和流水线设计成为一个NP难问题。另一方面，传统针对HLS指令优化的自动化搜索流程以单晶粒FPGA为目标，因此无法考虑每个晶粒上的资源约束以及跨晶粒布线引发的时序问题。此外，由于设计规模巨大，在指令优化过程中对每组配置生成的HLS设计进行布局合法化会导致过长的运行时间。为协同优化多晶粒FPGA上HLS设计的指令与布局，我们提出FADO框架，该框架基于多选择多维装箱问题形式化指令-布局协同搜索问题，并通过迭代优化流程求解。在每次指令搜索步骤中，采用延迟瓶颈引导的贪心算法搜索更高效的指令配置。对于布局规划，我们并未重复调用全局布局算法，而是实现了一种更高效的增量布局合法化算法。该算法主要利用最差适应在线装箱算法平衡布局，结合离线最佳适应递减重装箱算法压缩布局，并对跨晶粒边界的长线进行流水线处理。通过在混合数据流与非数据流内核的HLS设计上进行实验，FADO不仅实现了高度自动化的协同优化，其运行时间相比基于全局布局辅助的设计空间探索（DSE）缩短了693倍至4925倍，而且在Xilinx Alveo U250 FPGA上实现后，整体工作流执行时间提升了1.16倍至8.78倍。