Post-layout simulation provides accurate guidance for analog circuit design, but post-layout performance is hard to be directly optimized at early design stages. Prior work on analog circuit sizing often utilizes pre-layout simulation results as the optimization objective. In this work, we propose a post-layout-simulation-driven (post-simulation-driven for short) analog circuit sizing framework that directly optimizes the post-layout simulation performance. The framework integrates automated layout generation into the optimization loop of transistor sizing and leverages a coupled Bayesian optimization algorithm to search for the best post-simulation performance. Experimental results demonstrate that our framework can achieve over 20% better post-layout performance in competitive time than manual design and the method that only considers pre-layout optimization.

翻译：布局后仿真为模拟电路设计提供了精确的指导，但在早期设计阶段，布局后性能难以被直接优化。先前关于模拟电路尺寸优化的工作通常将布局前仿真结果作为优化目标。本文提出一种布局后仿真驱动（简称后仿真驱动）的模拟电路尺寸优化框架，该框架直接优化布局后仿真性能。该框架将自动布局生成集成到晶体管尺寸优化的循环中，并利用耦合贝叶斯优化算法搜索最佳后仿真性能。实验结果表明，与手工设计及仅考虑布局前优化的方法相比，本框架在具有竞争力的时间内可使布局后性能提升超过20%。