The relentless advancement of artificial intelligence (AI) and machine learning (ML) applications necessitates the development of specialized hardware accelerators capable of handling the increasing complexity and computational demands. Traditional computing architectures, based on the von Neumann model, are being outstripped by the requirements of contemporary AI/ML algorithms, leading to a surge in the creation of accelerators like the Graphcore Intelligence Processing Unit (IPU), Sambanova Reconfigurable Dataflow Unit (RDU), and enhanced GPU platforms. These hardware accelerators are characterized by their innovative data-flow architectures and other design optimizations that promise to deliver superior performance and energy efficiency for AI/ML tasks. This research provides a preliminary evaluation and comparison of these commercial AI/ML accelerators, delving into their hardware and software design features to discern their strengths and unique capabilities. By conducting a series of benchmark evaluations on common DNN operators and other AI/ML workloads, we aim to illuminate the advantages of data-flow architectures over conventional processor designs and offer insights into the performance trade-offs of each platform. The findings from our study will serve as a valuable reference for the design and performance expectations of research prototypes, thereby facilitating the development of next-generation hardware accelerators tailored for the ever-evolving landscape of AI/ML applications. Through this analysis, we aspire to contribute to the broader understanding of current accelerator technologies and to provide guidance for future innovations in the field.

翻译：人工智能（AI）与机器学习（ML）应用的持续进步，催生了能够处理日益增长的复杂性与计算需求的专用硬件加速器的研发需求。基于冯·诺依曼模型的传统计算架构已难以满足当代AI/ML算法的要求，从而推动了Graphcore智能处理单元（IPU）、Sambanova可重构数据流单元（RDU）以及增强型GPU平台等加速器的涌现。这些硬件加速器以创新的数据流架构及其他设计优化为特征，有望在AI/ML任务中实现卓越的性能与能效。本研究对上述商业AI/ML加速器进行了初步评估与对比，深入分析其硬件与软件设计特性，以揭示其优势与独特能力。通过针对常见DNN算子及其他AI/ML工作负载开展一系列基准测试评估，我们旨在阐明数据流架构相较于传统处理器设计的优势，并提出各平台性能权衡的见解。本研究的发现将为研究原型的性能预期与设计提供有价值的参考，进而推动面向不断演变的AI/ML应用场景的下一代硬件加速器的开发。通过这一分析，我们期望为当前加速器技术的广泛理解做出贡献，并为该领域的未来创新提供指导。