We present RTLScout, an autonomous system that combines LLM-driven agentic design with circuit-level synthesis optimization and arithmetic architecture sweeps. An LLM agent iteratively writes, evaluates, and refines RTL designs using tool calls, guided by quantitative PPA (power, performance, area) feedback from Yosys and OpenROAD. We introduce a multi-run elite pool framework, where the best designs and lessons learned seed subsequent agent runs. The pipeline comprises four complementary phases: agentic code optimization, agentic gate-level rewriting, arithmetic architecture sweeps, and an optional high-effort gate-level refinement pass. On an IEEE-754-compliant 16-bit floating-point multiplier with subnormal support, RTLScout reduces area by 35% and delay by 45% relative to a starting design synthesized in ASAP7 technology. Each phase provides distinct improvements, and high-effort gate-level optimization is most effective as a refinement of already well-optimized designs rather than a substitute for earlier stages. The resulting Pareto front outperforms a commercial-tool reference design on the same technology.

翻译：我们提出了RTLScout，一个将基于大语言模型（LLM）的智能体设计、电路级综合优化以及算术架构搜索相结合的自洽系统。LLM智能体通过工具调用迭代地编写、评估并优化RTL设计，并受来自Yosys和OpenROAD的量化PPA（功耗、性能、面积）反馈指导。我们引入了一个多轮精英池框架，其中最佳设计及经验教训将作为后续智能体运行的初始输入。该流水线包含四个互补阶段：智能体代码优化、智能体门级重写、算术架构搜索，以及可选的深度门级优化步骤。针对一个采用ASAP7工艺综合、符合IEEE-754标准的16位浮点乘法器（支持非规格化数），RTLScout相较于初始设计将面积减少了35%，延迟降低了45%。每个阶段均提供了独特的改进效果，而深度门级优化对于已充分优化的设计而言最有效，它应作为早期阶段的补充而非替代。最终得到的Pareto前沿在同一工艺上优于商业工具生成的参考设计。