Modular design is a key challenge for enabling large-scale reuse of hardware modules. Unlike software, however, hardware designs correspond to physical circuits and inherit constraints from them. Timing constraints -- which cycle a signal arrives, when an input is read -- and structural constraints -- how often a multiplier accepts new inputs -- are fundamental to hardware interfaces. Existing hardware design languages do not provide a way to encode these constraints; a user must read documentation, build scripts, or in the worst case, a module's implementation to understand how to use it. We present Filament, a language for modular hardware design that supports the specification and enforcement of timing and structural constraints for statically scheduled pipelines. Filament uses timeline types, which describe the intervals of clock-cycle time when a given signal is available or required. Filament enables safe composition of hardware modules, ensures that the resulting designs are correctly pipelined, and predictably lowers them to efficient hardware.

翻译：模块化设计是实现硬件模块大规模复用的关键挑战。然而，与软件不同，硬件设计对应物理电路并继承其约束条件。时序约束——信号在哪个时钟周期到达、输入何时被读取——以及结构约束——乘法器接受新输入的频率——是硬件接口的基础。现有硬件设计语言无法提供编码这些约束的手段；用户必须查阅文档、构建脚本，最坏情况下甚至需要阅读模块的实现才能理解其用法。我们提出Filament——一种支持静态调度流水线中时序与结构约束规范与强制的模块化硬件设计语言。Filament采用时间线类型描述给定信号可用或所需的时钟周期时间区间。Filament能够实现硬件模块的安全组合，确保最终设计的流水线正确性，并可预测地将其降级为高效硬件实现。