LLMs can generate SystemVerilog assertions (SVAs) from natural language specs, but single-pass outputs often lack functional coverage due to limited IC design understanding. We propose CoverAssert, an iterative framework that clusters semantic and AST-based structural features of assertions, maps them to specifications, and uses functional coverage feedback to guide LLMs in prioritizing uncovered points. Experiments on four open-source designs show that integrating CoverAssert with AssertLLM and Spec2Assertion improves average improvements of 9.57 % in branch coverage, 9.64 % in statement coverage, and 15.69 % in toggle coverage.

翻译：LLM可根据自然语言规范生成SystemVerilog断言（SVA），但单次输出常因缺乏对IC设计的深入理解而功能覆盖率不足。我们提出CoverAssert框架，该迭代框架对断言的语义特征和基于抽象语法树的结构特征进行聚类，将其映射到规范，并利用功能覆盖率反馈引导LLM优先处理未覆盖点。在四个开源设计上的实验表明，将CoverAssert与AssertLLM及Spec2Assertion集成后，分支覆盖率平均提升9.57%，语句覆盖率平均提升9.64%，翻转覆盖率平均提升15.69%。