LLMs can generate SystemVerilog assertions (SVAs) from natural language specs, but single-pass outputs often lack functional coverage due to limited IC design understanding. We propose CoverAssert, an iterative framework that clusters semantic and AST-based structural features of assertions, maps them to specifications, and uses functional coverage feedback to guide LLMs in prioritizing uncovered points. Experiments on four open-source designs show that integrating CoverAssert with AssertLLM and Spec2Assertion improves average improvements of 9.57 % in branch coverage, 9.64 % in statement coverage, and 15.69 % in toggle coverage.

翻译：LLM能够根据自然语言规格生成SystemVerilog断言（SVA），但由于对集成电路设计理解有限，单次输出往往缺乏功能覆盖率。我们提出CoverAssert框架，该框架通过聚类断言的语义与基于抽象语法树的结构特征，将其映射至规格说明，并利用功能覆盖率反馈引导LLM优先处理未覆盖点。在四个开源设计上的实验表明，将CoverAssert与AssertLLM及Spec2Assertion集成后，分别在分支覆盖率、语句覆盖率和翻转覆盖率上平均提升9.57%、9.64%和15.69%。