Ising Machine is a promising computing approach for solving combinatorial optimization problems. It is naturally suited for energy-saving and compact in-memory computing implementations with emerging memories. A na\"ive in-memory computing implementation of a quadratic Ising Machine requires an array of coupling weights that grows quadratically with problem size. However, the resources in such an approach are used inefficiently due to sparsity in practical optimization problems. We first show that this issue can be addressed by partitioning a coupling array into smaller sub-arrays. This technique, however, requires interconnecting subarrays; hence, we developed in-memory computing architecture for quadratic Ising Machines inspired by island-type field programmable gate arrays, which is the main contribution of our paper. We adapt open-source tools to optimize problem embedding and model routing overhead. Modeling results of benchmark problems for the developed architecture show up to 60x area improvement and faster operation than the baseline approach. Finally, we discuss algorithm/circuit co-design techniques for further improvements.

翻译：伊辛机是解决组合优化问题的一种有前景的计算方法。它天然适用于采用新兴存储器实现节能且紧凑的存内计算。二次伊辛机的朴素存内计算实现需要一组耦合权重，其规模随问题规模呈二次增长。然而，由于实际优化问题中的稀疏性，该方法中资源利用效率低下。我们首先证明，通过将耦合阵列划分为更小的子阵列可以解决这一问题。但这种技术需要互连子阵列；因此，我们受岛式现场可编程门阵列启发，开发了用于二次伊辛机的存内计算架构，这是本文的主要贡献。我们采用开源工具优化问题嵌入并建模路由开销。针对所开发架构的基准问题建模结果表明，与基线方法相比，面积效率提升高达60倍，且运行速度更快。最后，我们讨论了用于进一步改进的算法/电路协同设计技术。