Antiferromagnetic Tunnel Junctions (AFMTJs) offer picosecond switching and high integration density for in-memory computing, but their ultrafast dynamics and low tunnel magnetoresistance (TMR) make state-of-the-art MRAM interfaces unreliable. This work develops a device-circuit co-designed read/write interface optimized for AFMTJ behavior. Using a calibrated SPICE AFMTJ model as a baseline, we identify the limitations of conventional drivers and propose an asymmetric pulse driver (PD) for deterministic picosecond switching and a self-timed sense amplifier (STSA) with dynamic trip-point tuning for low-TMR sensing. Our experiments using SPICE and Monte Carlo evaluations demonstrate that the proposed circuits preserve AFMTJ latency and energy benefits while achieving robust read/write yield under realistic PVT and 3D integration parasitics, outperforming standard MRAM front-ends under the same conditions.

翻译：抗铁磁隧道结（AFMTJ）为内存计算提供了皮秒级开关速度与高集成密度，但其超快动力学特性与低隧道磁阻（TMR）使得现有最先进的MRAM接口可靠性不足。本研究开发了一种针对AFMTJ特性优化的电路协同设计读写接口。以经过校准的SPICE AFMTJ模型为基准，我们分析了传统驱动器的局限性，并提出了一种用于实现确定性皮秒开关的非对称脉冲驱动器（PD），以及一种具备动态阈值调节功能、适用于低TMR读取的自定时感测放大器（STSA）。通过SPICE仿真与蒙特卡洛评估实验表明，所提出的电路在保持AFMTJ延迟与能耗优势的同时，能够在实际工艺-电压-温度偏差及三维集成寄生效应下实现稳健的读写良率，其性能在同等条件下优于标准MRAM前端接口。