In this work, we report implementation and performance evaluation of memristor-driven fundamental logic gates, including NOT, AND, NAND, OR, NOR, and XOR, and novel and optimized design of the sequential logic circuits, such as D flip-flop, T-flip-flop, JK-flip-flop, and SR-flip-flop. The design, implementation, and optimization of these logic circuits were performed in SPECTRE in Cadence Virtuoso and integrated with 90 nm CMOS technology node. Additionally, we discuss an optimized design of memristor-driven logic gates and sequential logic circuits, and draw a comparative analysis with the other reported state-of-the-art work on sequential circuits. Moreover, the utilized memristor framework was experimentally pre-validated with the experimental data of Y2O3-based memristive devices, which shows significantly low values of variability during switching in both device-to-device (D2D) and cycle-to-cycle (C2C) operation. The performance metrics were calculated in terms of area, power, and delay of these sequential circuits and were found to be reduced by more than ~24%, 60%, and 58%, respectively, as compared to the other state-of-the-art work on sequential circuits. Therefore, the implemented memristor-based design significantly improves the performance of various logic designs, which makes it more area and power-efficient and shows the potential of memristor in designing various low-power, low-cost, ultrafast, and compact circuits.

翻译：本研究报道了忆阻器驱动基本逻辑门（包括NOT、AND、NAND、OR、NOR和XOR）的实现与性能评估，以及时序逻辑电路（如D触发器、T触发器、JK触发器和SR触发器）的创新优化设计。这些逻辑电路的设计、实现与优化均在Cadence Virtuoso的SPECTRE环境中完成，并集成于90纳米CMOS工艺节点。此外，我们讨论了忆阻器驱动逻辑门与时序逻辑电路的优化设计方案，并与已报道的其他时序电路前沿研究进行了对比分析。所采用的忆阻器框架已通过基于Y2O3的忆阻器件实验数据进行了预先实验验证，该器件在器件间（D2D）与循环间（C2C）操作切换过程中均表现出极低的性能波动值。通过面积、功耗和延迟等性能指标对时序电路进行评估，结果显示相较于其他时序电路前沿研究，本设计在上述指标上分别降低了约24%、60%和58%。因此，所实现的忆阻器基设计显著提升了各类逻辑电路的性能，使其更具面积与能效优势，展现了忆阻器在设计低功耗、低成本、超高速及紧凑型电路方面的巨大潜力。