LLM agents now write their own schematic and layout generators, run EDA tools, read the results, and fix the design. This "vibe tapeout" is becoming practical for analog circuits as well. This paper measures how far it has come in two settings. (A) On an open PDK (SKY130), a cloud LLM agent designed an 11-bit, 5.12-MS/s SAR ADC from its specification. The agents produced DRC- and LVS-clean macros and met the specification after parasitic extraction (PEX). In particular, under the condition in which the agent received a sanitized reference design derived from our 65-nm design (vibe porting), it produced the best layout in the shortest time. Its area was 1/1.6 to 1/2.8 of that of the conditions without a reference. This condition reached signoff without human intervention. The agents also identified the causes of post-PEX degradation (CDAC wiring coupling and common-mode-dependent comparator offset) by their own experiments. On the other hand, agents sometimes reported false passes, and verification independent of the design agent was essential. (B) A commercial PDK is under NDA and cannot be given to a cloud LLM. We therefore evaluated local LLMs running on university servers with a six-task benchmark on a commercial 65-nm CMOS PDK. Kimi K3 passed five of the six tasks, while MiniMax M3 passed two. Neither solved the debugging task, which requires finding the cause from symptoms. Finally, we discuss the prospects for extending vibe tapeout from ADCs to entire SoCs, and ask whether vibe tapeout is a dark age or a golden age for analog design. Our answer is that it is a golden age for designers who know what to verify.

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