FREESS (Free Educational Superscalar Simulator) is an open-source teaching environment for instruction-level parallelism in a RISC-V-inspired superscalar processor. It provides a compact, cycle-by-cycle view of register renaming, issue, execution, write-back, commit, and memory ordering in a Tomasulo-style machine. The simulator exposes the register map, free pool, instruction window, reorder buffer, and load/store queues in one textual representation, so the evolution of the hardware state can be followed on screen and reproduced on paper. Runtime parameters such as issue width, queue sizes, and functional-unit latencies can be changed easily, enabling direct comparison among alternative superscalar organizations. The tool has supported Advanced Computer Architecture teaching for about fifteen years and is publicly available on GitHub.

翻译：FREESS（Free Educational Superscalar Simulator）是一个面向RISC-V启发式超标量处理器指令级并行的开源教学环境。该仿真器以紧凑的逐周期视图展示Tomasulo架构中的寄存器重命名、发射、执行、写回、提交及内存排序过程。它通过单一文本表征同时呈现寄存器映射表、空闲池、指令窗口、重排序缓冲区和加载/存储队列，使硬件状态的演化过程可直观呈现在屏幕上并可复制记录于纸面。用户可方便地修改发射宽度、队列容量及功能单元延迟等运行时参数，实现不同超标量组织方式的直接对比。该工具已支持高级计算机架构教学约十五年，现于GitHub公开发布。