Multi-core neuromorphic systems typically use on-chip routers to transmit spikes among cores. These routers require significant memory resources and consume a large part of the overall system's energy budget. A promising alternative approach to using standard CMOS and SRAM-based routers is to exploit the features of memristive crossbar arrays and use them as programmable switch-matrices that route spikes. However, the scaling of these crossbar arrays presents physical challenges, such as `IR drop' on the metal lines due to the parasitic resistance, and leakage current accumulation on multiple active `off' memristors. While reliability challenges of this type have been extensively studied in synchronous systems for compute-in-memory matrix-vector multiplication (MVM) accelerators and storage class memory, little effort has been devoted so far to characterizing the scaling limits of memristor-based crossbar routers. In this paper, we study the challenges of memristive crossbar arrays, when used as routing channels to transmit spikes in asynchronous Spiking Neural Network (SNN) hardware. We validate our analytical findings with experimental results obtained from a 4K-ReRAM chip which demonstrate its functionality as a routing crossbar. We determine the functionality bounds on the routing due to the IR drop and leak problem, based both on experimental measurements, modeling and circuit simulations in a 22nm FDSOI technology. This work highlights the constraint of this approach and provides useful guidelines for engineering memristor properties in memristive crossbar routers for building multi-core asynchronous neuromorphic systems.

翻译：多核神经形态系统通常使用片上路由器在核间传输脉冲。这些路由器需要大量存储资源，并消耗系统总能量预算的很大一部分。一种替代标准CMOS和基于SRAM路由器的有前景方法是利用忆阻交叉阵列的特性，将其用作可编程开关矩阵来路由脉冲。然而，这些交叉阵列的扩展面临物理挑战，例如由寄生电阻引起的金属线上的“IR压降”，以及多个激活“关”态忆阻器上的漏电流累积。虽然此类可靠性挑战已在同步系统中针对存内计算矩阵向量乘法（MVM）加速器和存储级存储器得到广泛研究，但迄今为止，针对忆阻基交叉路由器的扩展极限特征化研究鲜有涉足。本文研究了忆阻交叉阵列在异步脉冲神经网络（SNN）硬件中用作脉冲传输路由通道时面临的挑战。我们通过从4K-ReRAM芯片获得的实验结果验证了分析结果，证明了其作为路由交叉阵列的功能性。基于22nm FDSOI技术中的实验测量、建模和电路仿真，我们确定了因IR压降和漏电问题导致的路由功能边界。本研究强调了该方法的局限性，并为在构建多核异步神经形态系统的忆阻交叉路由器中工程化忆阻器特性提供了有用指导准则。