Caches at CPU nodes in disaggregated memory architectures amortize the high data access latency over the network. However, such caches are fundamentally unable to improve performance for workloads requiring pointer traversals across linked data structures. We argue for accelerating these pointer traversals closer to disaggregated memory, in a manner that preserves expressiveness for supporting various linked structures, ensures energy efficiency and performance, and supports distributed execution. We design CHASE to meet all the above requirements for pointer-traversal workloads on rack-scale disaggregated memory through the principled use of FPGAbased SmartNICs and programmable network switches. Our evaluation of CHASE shows that it enables low-latency, highthroughput, and energy-efficient execution for a wide range of common pointer traversal workloads on disaggregated memory that fare poorly with caching alone.

翻译：在分离内存架构中，CPU节点的缓存通过网络摊销了高数据访问延迟。然而，此类缓存从根本上无法提升需要跨链接数据结构进行指针遍历的工作负载的性能。我们主张在更靠近分离内存的位置加速这些指针遍历，同时保持对多种链接结构支持的表现力、确保能效与性能，并支持分布式执行。我们设计了CHASE，通过原则性地使用基于FPGA的智能网卡和可编程网络交换机，满足机架级分离内存上指针遍历工作负载的所有上述要求。对CHASE的评估表明，它为分离内存中常见的多种指针遍历工作负载（单独依靠缓存时性能较差）实现了低延迟、高吞吐量和高效能耗的执行。