Globalization in the semiconductor industry enables fabless design houses to reduce their costs, save time, and make use of newer technologies. However, the offshoring of Integrated Circuit (IC) fabrication has negative sides, including threats such as Hardware Trojans (HTs) - a type of malicious logic that is not trivial to detect. One aspect of IC design that is not affected by globalization is the need for thorough verification. Verification engineers devise complex assets to make sure designs are bug-free, including assertions. This knowledge is typically not reused once verification is over. The premise of this paper is that verification assets that already exist can be turned into effective security checkers for HT detection. For this purpose, we show how assertions can be used as online monitors. To this end, we propose a security metric and an assertion selection flow that leverages Cadence JasperGold Security Path Verification (SPV). The experimental results show that our approach scales for industry-size circuits by analyzing more than 100 assertions for different Intellectual Properties (IPs) of the OpenTitan System-on-Chip (SoC). Moreover, our detection solution is pragmatic since it does not rely on the HT activation mechanism.

翻译：半导体产业的全球化使无晶圆厂设计公司能够降低成本、节省时间并采用更先进的技术。然而，集成电路（IC）制造的离岸化也带来了负面影响，包括诸如硬件木马（HT）等威胁——一种难以检测的恶意逻辑。IC设计中不受全球化影响的环节之一是对彻底验证的需求。验证工程师设计复杂的资产（包括断言）以确保设计无缺陷。这些知识通常在验证结束后不会被复用。本文的前提是，已有的验证资产可以转化为有效的HT检测安全检查器。为此，我们展示了如何将断言用作在线监控器。我们提出了一种安全度量标准和一个利用Cadence JasperGold安全路径验证（SPV）的断言选择流程。实验结果表明，我们的方法能够通过分析OpenTitan系统级芯片（SoC）不同知识产权核（IP）的100多个断言，扩展到工业规模电路。此外，我们的检测方案具有实用性，因为它不依赖于HT激活机制。