Quantum error-correcting codes (QECCs) can eliminate the negative effects of quantum noise, the major obstacle to the execution of quantum algorithms. However, realizing practical quantum error correction (QEC) requires resolving many challenges to implement a high-performance real-time decoding system. Many decoding algorithms have been proposed and optimized in the past few decades, of which neural network (NNs) based solutions have drawn an increasing amount of attention due to their high efficiency. Unfortunately, previous works on neural decoders are still at an early stage and have only relatively simple architectures, which makes them unsuitable for practical QEC. In this work, we propose a scalable, fast, and programmable neural decoding system to meet the requirements of FTQEC for rotated surface codes (RSC). Firstly, we propose a hardware-efficient NN decoding algorithm with relatively low complexity and high accuracy. Secondly, we develop a customized hardware decoder with architectural optimizations to reduce latency. Thirdly, our proposed programmable architecture boosts the scalability and flexibility of the decoder by maximizing parallelism. Fourthly, we build an FPGA-based decoding system with integrated control hardware for evaluation. Our $L=5$ ($L$ is the code distance) decoder achieves an extremely low decoding latency of 197 ns, and the $L=7$ configuration also requires only 1.136 $\mu$s, both taking $2L$ rounds of syndrome measurements. The accuracy results of our system are close to minimum weight perfect matching (MWPM). Furthermore, our programmable architecture reduces hardware resource consumption by up to $3.0\times$ with only a small latency loss. We validated our approach in real-world scenarios by conducting a proof-of-concept benchmark with practical noise models, including one derived from experimental data gathered from physical hardware.

翻译：量子纠错码（QECCs）可以消除量子噪声（执行量子算法的主要障碍）的负面影响。然而，实现实用的量子纠错（QEC）需要解决许多挑战，以构建高性能的实时译码系统。过去几十年中，已提出并优化了许多译码算法，其中基于神经网络（NN）的解决方案因其高效率而受到越来越多的关注。遗憾的是，先前关于神经译码器的工作仍处于早期阶段，且架构相对简单，因而无法适用于实际QEC场景。在本工作中，我们提出了一种可扩展、快速且可编程的神经译码系统，以满足旋转表面码（RSC）对容错量子计算（FTQEC）的需求。首先，我们提出了一种硬件高效的NN译码算法，具有相对较低的复杂度和高精度。其次，我们开发了一种定制化硬件译码器，通过架构优化来降低延迟。第三，我们提出的可编程架构通过最大化并行度，提升了译码器的可扩展性和灵活性。第四，我们构建了一个基于FPGA的译码系统，集成控制硬件用于评估。我们的$L=5$（$L$为码距）译码器实现了低至197 ns的译码延迟，而$L=7$配置也仅需1.136 μs，两者均需$2L$轮症状测量。系统的精度结果接近最小权重完美匹配（MWPM）。此外，我们的可编程架构可将硬件资源消耗降低高达$3.0\times$，且仅损失少量延迟。我们通过使用实际噪声模型（包括从物理硬件实验数据中导出的模型）进行概念验证基准测试，在真实场景中验证了该方法。