The development of sixth-generation (6G) mobile networks imposes unprecedented latency and reliability demands on multiple-input multiple-output (MIMO) communication systems, a key enabler of high-speed radio access. Recently, deep unfolding-based detectors, which map iterative algorithms onto neural network architectures, have emerged as a promising approach, combining the strengths of model-driven and data-driven methods to achieve high detection accuracy with relatively low complexity. However, algorithmic innovation alone is insufficient; software-hardware co-design is essential to meet the extreme latency requirements of 6G (i.e., 0.1 milliseconds). This motivates us to propose leveraging in-memory computing, which is an analog computing technology that integrates memory and computation within memristor circuits, to perform the intensive matrix-vector multiplication (MVM) operations inherent in deep MIMO detection at the nanosecond scale. Specifically, we introduce a novel architecture, called the deep in-memory MIMO (IM-MIMO) detector, characterized by two key features. First, each of its cascaded computational blocks is decomposed into channel-dependent and channel-independent neural network modules. Such a design minimizes the latency of memristor reprogramming in response to channel variations, which significantly exceeds computation time. Second, we develop a customized detector-training method that exploits prior knowledge of memristor-value statistics to enhance robustness against programming noise. Furthermore, we conduct a comprehensive analysis of the IM-MIMO detector's performance, evaluating detection accuracy, processing latency, and hardware complexity. Our study quantifies detection error as a function of various factors, including channel noise, memristor programming noise, and neural network size.

翻译：第六代（6G）移动网络的发展对多输入多输出（MIMO）通信系统——高速无线接入的关键使能技术——提出了前所未有的时延与可靠性要求。近年来，将迭代算法映射至神经网络架构的深度展开检测器成为了一种颇具前景的方法，其融合了模型驱动与数据驱动方法的优势，以相对较低的复杂度实现了高检测精度。然而，仅凭借算法创新是不够的；为满足6G极端时延要求（即0.1毫秒），软件-硬件协同设计至关重要。这促使我们提出利用存内计算——一种将存储与计算集成于忆阻器电路中的模拟计算技术——在纳秒级尺度上执行深度MIMO检测中固有的密集型矩阵-向量乘法（MVM）运算。具体而言，我们提出了一种新颖的架构，称为深度存内MIMO（IM-MIMO）检测器，其具有两个关键特征：首先，其每个级联计算块被分解为信道相关与信道无关的神经网络模块，这种设计将应对信道变化时忆阻器重编程的时延降至最低——该时延远超计算时间；其次，我们开发了一种定制化的检测器训练方法，利用忆阻器值统计特性的先验知识来增强对编程噪声的鲁棒性。此外，我们对IM-MIMO检测器的性能进行了全面分析，评估了检测精度、处理时延及硬件复杂度。我们的研究将检测误差量化为多种因素的函数，包括信道噪声、忆阻器编程噪声及神经网络规模。