There is substantial interest in the use of machine learning (ML)-based techniques throughout the electronic computer-aided design (CAD) flow, particularly methods based on deep learning. However, while deep learning methods have achieved state-of-the-art performance in several applications, recent work has demonstrated that neural networks are generally vulnerable to small, carefully chosen perturbations of their input (e.g. a single pixel change in an image). In this work, we investigate robustness in the context of ML-based EDA tools -- particularly for congestion prediction. As far as we are aware, we are the first to explore this concept in the context of ML-based EDA. We first describe a novel notion of imperceptibility designed specifically for VLSI layout problems defined on netlists and cell placements. Our definition of imperceptibility is characterized by a guarantee that a perturbation to a layout will not alter its global routing. We then demonstrate that state-of-the-art CNN and GNN-based congestion models exhibit brittleness to imperceptible perturbations. Namely, we show that when a small number of cells (e.g. 1%-5% of cells) have their positions shifted such that a measure of global congestion is guaranteed to remain unaffected (e.g. 1% of the design adversarially shifted by 0.001% of the layout space results in a predicted decrease in congestion of up to 90%, while no change in congestion is implied by the perturbation). In other words, the quality of a predictor can be made arbitrarily poor (i.e. can be made to predict that a design is "congestion-free") for an arbitrary input layout. Next, we describe a simple technique to train predictors that improves robustness to these perturbations. Our work indicates that CAD engineers should be cautious when integrating neural network-based mechanisms in EDA flows to ensure robust and high-quality results.

翻译：在电子计算机辅助设计（CAD）流程中，基于机器学习（ML）的技术（尤其是深度学习方法）引起了广泛关注。然而，尽管深度学习方法在多个应用中取得了最先进的性能，近期研究已表明神经网络通常容易受到微小、精心选择的输入扰动的影响（例如图像中单个像素的改变）。在本研究中，我们探讨了基于ML的电子设计自动化（EDA）工具中的鲁棒性问题——特别是针对拥塞预测。据我们所知，我们是首个在基于ML的EDA背景下探索这一概念的研究。我们首先提出了一种新颖的“不可察觉性”定义，专门针对基于网表和单元布局的超大规模集成电路（VLSI）布局问题。我们的不可察觉性定义以“布局扰动不会改变其全局布线”的保证为特征。随后，我们证明了当前最先进的基于CNN和GNN的拥塞模型对不可察觉扰动表现出脆弱性。具体而言，我们表明：当少量单元（例如1%-5%的单元）被移位到保证全局拥塞度量不受影响的位置时（例如，设计中的1%单元被对抗性移动0.001%的布局空间，会导致预测拥塞降低高达90%，而该扰动实际上并未改变真实拥塞）。换言之，对于任意输入布局，预测器的质量可以被任意降低（即可以使其预测设计“无拥塞”）。接下来，我们描述了一种简单的训练方法，以提升预测器对这些扰动的鲁棒性。我们的研究表明，CAD工程师在设计集成神经网络机制的EDA流程时需谨慎，以确保获得鲁棒且高质量的结果。