Logic Obfuscation is a well renowned design-for-trust solution to protect an Integrated Circuit (IC) from unauthorized use and illegal overproduction by including key-gates to lock the design. This is particularly necessary for ICs manufactured at untrusted third-party foundries getting exposed to security threats. In the past, several logic obfuscation methodologies have been proposed that are vulnerable to attacks such as the Boolean Satisfiability Attack. Many of these techniques are implemented at the gate level that may involve expensive re-synthesis cycles. In this paper, we present an interconnect obfuscation scheme at the Register-Transfer Level (RTL) using Switch Boxes (SBs) constructed of Polymorphic Transistors. A polymorphic SB can be designed using the same transistor count as its Complementary-Metal-Oxide-Semiconductor based counterpart, thereby no increased area in comparison, but serving as an advantage in having more key-bit combinations for an attacker to correctly identify and unlock each polymorphic SB. Security-aware high-level synthesis algorithms have also been presented to increase RTL interconnects to Functional Units impacting multiple outputs such that when a polymorphic SB is strategically inserted, those outputs would be corrupted upon incorrect key-bit identification. Finally, we run the SMT (Satisfiability Modulo Theories)-based RTL Logic Attack on the obfuscated design to examine its robustness.

翻译：逻辑混淆是一种广为人知的面向信任的设计解决方案，通过引入密钥门来锁定集成电路（IC）设计，以防止其被未经授权使用和非法过量生产。这对于在不可信的第三方代工厂制造并面临安全威胁威胁的IC尤为必要。过去提出的多种逻辑混淆方法容易受到布尔可满足性攻击等威胁，且许多技术实现在门级层面，可能涉及昂贵的重综合周期。本文提出了一种在寄存器传输级（RTL）使用多态晶体管构建的开关盒（SB）的互连混淆方案。多态开关盒可采用与互补金属氧化物半导体（CMOS）基对应物相同的晶体管数量设计，因此不增加面积，但优势在于能够为攻击者提供更多密钥位组合，使其需要正确识别并解锁每个多态开关盒。我们还提出了安全感知的高层次综合算法，以增加通向功能单元的RTL互连对多输出的影响，从而当策略性地插入多态开关盒时，若密钥位识别错误，这些输出将被破坏。最后，我们采用基于可满足性模理论（SMT）的RTL逻辑攻击对混淆设计进行鲁棒性测试。