Bit Layer Multiplier Accumulator (BLMAC) is an efficient method to perform dot products without multiplications that exploits the bit level sparsity of the weights. A total of 1,980,000 low, high, band pass and band stop type I FIR filters were generated by systematically sweeping through the cut off frequencies and by varying the number of taps from 55 to 255. After their coefficients were quantized to 16 bits, applying the filter using a BLMAC required, on average, from ~123.3 to ~513.6 additions, depending on the number of taps. A BLMAC dot product machine, specialised for 127 taps FIR filters, was designed for AMD FPGAs. The design footprint is ~110 LUTs, including coefficient and sample storage and is able to apply the filter in ~232 clock cycles on average. This implies a filtering rate of 1.4-3.4 Msamples/s, depending on the FPGA family.

翻译：位层乘法累加器（BLMAC）是一种无需乘法即可执行点积的高效方法，它利用权重的位级稀疏性。通过系统扫描截止频率并将抽头数从55变化到255，共生成1,980,000个低通、高通、带通和带阻I型FIR滤波器。当其系数量化为16位后，使用BLMAC应用滤波器平均需要约123.3至513.6次加法，具体取决于抽头数。专为127抽头FIR滤波器设计的BLMAC点积运算器基于AMD FPGA实现，设计资源占用约110个查找表（LUT），包含系数和样本存储，平均约232个时钟周期即可完成滤波。这意味着滤波速率为1.4-3.4兆样本/秒，具体取决于FPGA系列。