This paper tackles the challenges of implementing few-shot learning on embedded systems, specifically FPGA SoCs, a vital approach for adapting to diverse classification tasks, especially when the costs of data acquisition or labeling prove to be prohibitively high. Our contributions encompass the development of an end-to-end open-source pipeline for a few-shot learning platform for object classification on a FPGA SoCs. The pipeline is built on top of the Tensil open-source framework, facilitating the design, training, evaluation, and deployment of DNN backbones tailored for few-shot learning. Additionally, we showcase our work's potential by building and deploying a low-power, low-latency demonstrator trained on the MiniImageNet dataset with a dataflow architecture. The proposed system has a latency of 30 ms while consuming 6.2 W on the PYNQ-Z1 board.

翻译：本文解决了在嵌入式系统（特别是FPGA SoC）上实现小样本学习的挑战，这是适应多样化分类任务的关键方法，尤其在数据采集或标注成本过高的情况下。我们的贡献包括为FPGA SoC上的目标分类小样本学习平台开发了一套端到端的开源流水线。该流水线基于Tensil开源框架构建，支持针对小样本学习的深度神经网络主干网络的设计、训练、评估和部署。此外，我们通过构建并部署一个基于MiniImageNet数据集、采用数据流架构的低功耗低延迟演示器，展示了本工作的潜力。所提系统在PYNQ-Z1开发板上实现了30毫秒的延迟，功耗为6.2瓦。