This paper presents RTLFixer, a novel framework enabling automatic syntax errors fixing for Verilog code with Large Language Models (LLMs). Despite LLM's promising capabilities, our analysis indicates that approximately 55% of errors in LLM-generated Verilog are syntax-related, leading to compilation failures. To tackle this issue, we introduce a novel debugging framework that employs Retrieval-Augmented Generation (RAG) and ReAct prompting, enabling LLMs to act as autonomous agents in interactively debugging the code with feedback. This framework demonstrates exceptional proficiency in resolving syntax errors, successfully correcting about 98.5% of compilation errors in our debugging dataset, comprising 212 erroneous implementations derived from the VerilogEval benchmark. Our method leads to 32.3% and 10.1% increase in pass@1 success rates in the VerilogEval-Machine and VerilogEval-Human benchmarks, respectively.

翻译：本文提出RTLFixer，一种利用大语言模型（LLMs）自动修复Verilog代码语法错误的新型框架。尽管LLMs展现出强大的能力，但我们分析表明，LLMs生成的Verilog代码中约55%的错误与语法相关，导致编译失败。为解决此问题，我们引入了一个新颖的调试框架，该框架采用检索增强生成（RAG）和ReAct提示技术，使LLMs能够作为自主代理，根据反馈交互式调试代码。该框架在解决语法错误方面表现出卓越能力，成功修复了我们调试数据集中约98.5%的编译错误，该数据集包含从VerilogEval基准测试中提取的212个有误实现。我们的方法在VerilogEval-Machine和VerilogEval-Human基准测试中分别使pass@1成功率提升了32.3%和10.1%。