To alleviate the performance and energy overheads of contemporary applications with large data footprints, we propose the Two Level Perceptron (TLP) predictor, a neural mechanism that effectively combines predicting whether an access will be off-chip with adaptive prefetch filtering at the first-level data cache (L1D). TLP is composed of two connected microarchitectural perceptron predictors, named First Level Predictor (FLP) and Second Level Predictor (SLP). FLP performs accurate off-chip prediction by using several program features based on virtual addresses and a novel selective delay component. The novelty of SLP relies on leveraging off-chip prediction to drive L1D prefetch filtering by using physical addresses and the FLP prediction as features. TLP constitutes the first hardware proposal targeting both off-chip prediction and prefetch filtering using a multi-level perceptron hardware approach. TLP only requires 7KB of storage. To demonstrate the benefits of TLP we compare its performance with state-of-the-art approaches using off-chip prediction and prefetch filtering on a wide range of single-core and multi-core workloads. Our experiments show that TLP reduces the average DRAM transactions by 30.7% and 17.7%, as compared to a baseline using state-of-the-art cache prefetchers but no off-chip prediction mechanism, across the single-core and multi-core workloads, respectively, while recent work significantly increases DRAM transactions. As a result, TLP achieves geometric mean performance speedups of 6.2% and 11.8% across single-core and multi-core workloads, respectively. In addition, our evaluation demonstrates that TLP is effective independently of the L1D prefetching logic.

翻译：为缓解数据足迹较大的现代应用所面临的性能和能耗开销问题，我们提出两级感知器（TLP）预测器——一种神经网络机制，该机制有效结合了访问是否会在片外发生的预测与一级数据缓存（L1D）的自适应预取过滤。TLP由两个相互连接的微架构感知器预测器组成，分别称为第一级预测器（FLP）和第二级预测器（SLP）。FLP通过利用基于虚拟地址的多个程序特征以及一个新颖的选择性延迟组件，实现准确的片外预测。SLP的创新之处在于利用片外预测来驱动L1D预取过滤，其以物理地址和FLP预测结果作为特征。TLP是首个采用多级感知器硬件方法同时实现片外预测与预取过滤的硬件设计方案。TLP仅需7KB存储空间。为展示TLP的优势，我们在广泛范围的单核与多核工作负载上，将其与采用片外预测和预取过滤的现有最优方法进行性能对比。实验表明：与使用当前最优缓存预取器但不含片外预测机制的基线方案相比，TLP在单核与多核工作负载上分别平均减少30.7%和17.7%的DRAM事务量，而近期相关研究则显著增加了DRAM事务量。因此，TLP在单核与多核工作负载上分别实现了6.2%和11.8%的几何平均性能加速比。此外，评估结果表明TLP的有效性独立于L1D预取逻辑。