Current systolic arrays still suffer from low performance and PE utilization on many real workloads due to the mismatch between the fixed array topology and diverse DNN kernels. We present ReDas, a flexible and lightweight systolic array that can adapt to various DNN models by supporting dynamic fine-grained reshaping and multiple dataflows. The key idea is to construct reconfigurable roundabout data paths using only the short connections between neighbor PEs. The array with 128$\times$128 size supports 129 different logical shapes and 3 dataflows (IS/OS/WS). Experiments on DNN models of MLPerf demonstrate that ReDas can achieve 3.09x speedup on average compared to state-of-the-art work.

翻译：摘要：当前脉动阵列因固定拓扑结构与多样化深度神经网络（DNN）核之间的不匹配，在众多实际工作负载中仍面临性能低下及处理单元（PE）利用率不足的问题。本文提出ReDas——一种灵活轻量级的脉动阵列，通过支持动态细粒度重构与多种数据流，可适配各类DNN模型。其核心思想是仅利用相邻PE间的短连线构建可重构迂回数据通路。该128×128尺寸阵列支持129种不同逻辑形态及三种数据流（输入静态/输出静态/权重静态）。基于MLPerf DNN模型的实验表明，与现有最优方案相比，ReDas可平均实现3.09倍加速。