With the widespread use of deep neural networks(DNNs) in intelligent systems, DNN accelerators with high performance and energy efficiency are greatly demanded. As one of the feasible processing-in-memory(PIM) architectures, 3D-stacked-DRAM-based PIM(DRAM-PIM) architecture enables large-capacity memory and low-cost memory access, which is a promising solution for DNN accelerators with better performance and energy efficiency. However, the low-cost characteristics of stacked DRAM and the distributed manner of memory access and data storing require us to rebalance the hardware design and DNN mapping. In this paper, we propose NicePIM to efficiently explore the design space of hardware architecture and DNN mapping of DRAM-PIM accelerators, which consists of three key components: PIM-Tuner, PIM-Mapper and Data-Scheduler. PIM-Tuner optimizes the hardware configurations leveraging a DNN model for classifying area-compliant architectures and a deep kernel learning model for identifying better hardware parameters. PIM-Mapper explores a variety of DNN mapping configurations, including parallelism between branches of DNN, DNN layer partitioning, DRAM capacity allocation and data layout pattern in DRAM to generate high-hardware-utilization DNN mapping schemes for various hardware configurations. The Data-Scheduler employs an integer-linear-programming-based data scheduling algorithm to alleviate the inter-PIM-node communication overhead of data-sharing brought by DNN layer partitioning. Experimental results demonstrate that NicePIM can optimize hardware configurations for DRAM-PIM systems effectively and can generate high-quality DNN mapping schemes with latency and energy cost reduced by 37% and 28% on average respectively compared to the baseline method.

翻译：随着深度神经网络（DNN）在智能系统中的广泛应用，对高性能、高能效的DNN加速器需求日益迫切。作为可行的存内处理（PIM）架构之一，基于3D堆叠DRAM的PIM（DRAM-PIM）架构兼顾大容量存储与低开销内存访问，是构建兼具性能与能效优势的DNN加速器的理想方案。然而，堆叠DRAM的低成本特性及其分布式访存与数据存储方式，要求我们重新平衡硬件设计与DNN映射。本文提出NicePIM，旨在高效探索DRAM-PIM加速器的硬件架构与DNN映射设计空间，包含三大核心组件：PIM-Tuner、PIM-Mapper和Data-Scheduler。PIM-Tuner通过构建分类合规面积架构的DNN模型与辨识更优硬件参数的深度核学习模型，优化硬件配置。PIM-Mapper探索多维度DNN映射配置，包括DNN分支间并行度、DNN层划分、DRAM容量分配及数据布局模式，为各类硬件配置生成高硬件利用率的DNN映射方案。Data-Scheduler采用基于整数线性规划的数据调度算法，缓解DNN层划分带来的跨PIM节点数据共享通信开销。实验表明，相较于基准方法，NicePIM可有效优化DRAM-PIM系统的硬件配置，并生成高质量的DNN映射方案，使延迟与能耗分别平均降低37%和28%。