A time-efficient and comprehensive verification is a fundamental part of the design process for modern computing platforms, and it becomes ever more important and critical to optimize as the latter get ever more complex. SupeRFIVe is a methodology for the functional verification of superscalar processors that leverages an instruction set simulator to validate their correctness according to a simulation-based approach, interfacing a testbench for the design under test with the instruction set simulator by means of socket communication. We demonstrate the effectiveness of the SupeRFIVe methodology by applying it to verify the functional correctness of a RISC-V dual-issue superscalar CPU, leveraging the state-of-the-art RISC-V instruction set simulator Spike and executing a set of benchmark applications from the open literature.

翻译：高效且全面的验证是现代计算平台设计流程的基础环节，随着平台复杂度的不断提升，其重要性日益凸显且优化需求愈发关键。SupeRFIVe是一种针对超标量处理器的功能验证方法，该方法基于模拟验证范式，通过套接字通信将待测设计的测试平台与指令集模拟器相连接，从而利用指令集模拟器验证处理器的正确性。我们通过应用SupeRFIVe方法验证一款RISC-V双发射超标量CPU的功能正确性，展示了该方法的有效性。验证过程中采用了先进的RISC-V指令集模拟器Spike，并执行了来自公开文献的一组基准测试程序。