While side-channel leakage is traditionally evaluated from a fabricated chip, it is more time-efficient and cost-effective to do so during the design phase of the chip. We present a methodology to rank the gates of a design according to their contribution to the side-channel leakage of the chip. The methodology relies on logic synthesis, logic simulation, gate-level power estimation, and gate leakage assessment to compute a ranking. The ranking metric can be defined as a specific test by correlating gate-level activity with a leakage model, or else as a non-specific test by evaluating gate-level activity in response to distinct test vector groups. Our results show that only a minority of the gates in a design contribute most of the side-channel leakage. We demonstrate this property for several designs, including a hardware AES coprocessor and a cryptographic hardware/software interface in a five-stage pipelined RISC processor.

翻译：虽然侧道渗漏传统上是从制造的芯片中评估的,但在芯片的设计阶段这样做更具有时间效率和成本效益。我们提出一种方法,根据对芯片侧道渗漏的贡献来排列设计门。这种方法依靠逻辑合成、逻辑模拟、门级功率估计和门漏漏漏评估来计算等级。分级指标可以定义为一项具体测试,将门级活动与渗漏模型联系起来,或者通过根据不同的测试矢量组评估门级活动来进行非特定测试。我们的结果显示,在设计中,只有少数门有助于侧道渗漏。我们为若干设计展示了这种特性,包括五级输油管的RISC处理器的硬件AES处理器和密码处理硬件/软件界面。