This paper presents EPAC, a RISC-V-based accelerator chip developed within the European Processor Initiative (EPI) as part of a multi-year, multi-partner effort to build a European HPC processor ecosystem. EPAC is implemented in GlobalFoundries 22FDX (GF22FDX) technology, covers an area of 27 sq mm with approximately 0.3 billion transistors, and integrates three distinct RISC-V compute tiles targeting different workload classes: VEC, a vector processing tile for double-precision HPC workloads; STX, a many-core tile optimized for stencil and machine learning computations; and VRP, a variable-precision tile for iterative numerical solvers requiring extended floating-point formats. All tiles are connected through a Coherent Hub Interface (CHI) based network-on-chip with a distributed L2 cache system and communicate with external memory via a SerDes link. The chip was taped out in GF22FDX technology and successfully brought up, with all major IP blocks validated. This paper describes the architecture of each tile and the uncore infrastructure, the integration and physical implementation process, and the board-level bring-up activities. It also reflects on the engineering and coordination lessons learned from a full chip design effort distributed across academic and industrial partners in Europe.

翻译：本文介绍了EPAC，这是一款基于RISC-V架构的加速器芯片，作为欧洲处理器倡议（EPI）的一部分，是多年、多方合作构建欧洲HPC处理器生态系统的成果。EPAC采用格罗方德22FDX（GF22FDX）工艺实现，面积约27平方毫米，集成约3亿晶体管，并整合了三个针对不同负载类型的RISC-V计算单元：VEC——面向双精度HPC负载的向量处理单元；STX——为模板计算和机器学习计算优化的众核单元；以及VRP——适用于需要扩展浮点数格式的迭代数值求解器的可变精度单元。所有单元均通过基于CHI一致性集线接口的片上网络互联，并配备分布式L2缓存系统，通过SerDes链路与外部存储器通信。该芯片采用GF22FDX工艺流片并成功上电，所有主要IP模块均已通过验证。本文描述了各计算单元及非核心基础设施的架构、集成与物理实现过程，以及板级启动调试活动。同时，本文还反思了在设计过程中，由欧洲学术界和工业界合作伙伴共同参与的完整芯片设计工程所积累的经验与协调工作的教训。