Optimizing Register Transfer Level (RTL) code is a critical step in Electronic Design Automation (EDA) for improving power, performance, and area (PPA). We present CODMAS (Collaborative Optimization via a Dialectic Multi-Agent System), a framework that combines structured dialectic reasoning with domain-aware code generation and deterministic evaluation to automate RTL optimization. At the core of CODMAS are two dialectic agents: the Articulator, inspired by rubber-duck debugging, which articulates stepwise transformation plans and exposes latent assumptions; and the Hypothesis Partner, which predicts outcomes and reconciles deviations between expected and actual behavior to guide targeted refinements. These agents direct a Domain-Specific Coding Agent (DCA) to generate architecture-aware Verilog edits and a Code Evaluation Agent (CEA) to verify syntax, functionality, and PPA metrics. We introduce RTLOPT, a benchmark of 120 Verilog triples (unoptimized, optimized, testbench) for pipelining and clock-gating transformations. Across proprietary and open LLMs, CODMAS achieves ~25% reduction in critical path delay for pipelining and ~22% power reduction for clock gating, while reducing functional and compilation failures compared to strong prompting and agentic baselines. These results demonstrate that structured multi-agent reasoning can significantly enhance automated RTL optimization and scale to more complex designs and broader optimization tasks.

翻译：优化寄存器传输级（RTL）代码是电子设计自动化（EDA）中提升功耗、性能和面积（PPA）的关键步骤。我们提出CODMAS（基于辩证多智能体系统的协同优化框架），该框架结合了结构化辩证推理、领域感知的代码生成与确定性评估，以实现RTL优化的自动化。CODMAS的核心是两个辩证智能体：受“橡皮鸭调试法”启发的阐述者（Articulator），负责阐述逐步转换计划并揭示潜在假设；以及假设伙伴（Hypothesis Partner），负责预测结果并调和预期行为与实际行为之间的偏差，以指导针对性改进。这些智能体指导一个领域特定编码智能体（DCA）生成具备架构感知的Verilog代码编辑，并指导一个代码评估智能体（CEA）验证语法、功能及PPA指标。我们引入了RTLOPT基准测试集，包含120个用于流水线和时钟门控转换的Verilog三元组（未优化、已优化、测试平台）。在专有和开源大语言模型上，CODMAS在流水线优化中实现了约25%的关键路径延迟降低，在时钟门控中实现了约22%的功耗降低，同时相比强提示方法和智能体基线，减少了功能性和编译失败。这些结果表明，结构化的多智能体推理能够显著增强自动化RTL优化能力，并可扩展至更复杂的设计和更广泛的优化任务。