Logic synthesis is the first and most vital step in chip design. This steps converts a chip specification written in a hardware description language (such as Verilog) into an optimized implementation using Boolean logic gates. State-of-the-art logic synthesis algorithms have a large number of logic minimization heuristics, typically applied sequentially based on human experience and intuition. The choice of the order greatly impacts the quality (e.g., area and delay) of the synthesized circuit. In this paper, we propose INVICTUS, a model-based offline reinforcement learning (RL) solution that automatically generates a sequence of logic minimization heuristics ("synthesis recipe") based on a training dataset of previously seen designs. A key challenge is that new designs can range from being very similar to past designs (e.g., adders and multipliers) to being completely novel (e.g., new processor instructions). %Compared to prior work, INVICTUS is the first solution that uses a mix of RL and search methods joint with an online out-of-distribution detector to generate synthesis recipes over a wide range of benchmarks. Our results demonstrate significant improvement in area-delay product (ADP) of synthesized circuits with up to 30\% improvement over state-of-the-art techniques. Moreover, INVICTUS achieves up to $6.3\times$ runtime reduction (iso-ADP) compared to the state-of-the-art.

翻译：逻辑综合是芯片设计中最首要且关键的步骤。该步骤将用硬件描述语言（如Verilog）编写的芯片规范转化为基于布尔逻辑门实现的优化方案。当前最先进的逻辑综合算法包含大量逻辑最小化启发式方法，通常依据人类经验与直觉顺序应用。这些方法的执行顺序对综合后电路的质量（如面积、延迟）具有显著影响。本文提出INVICTUS——一种基于模型的离线强化学习（RL）方案，能够通过先前设计案例的训练数据集自动生成逻辑最小化启发式方法的执行序列（即“综合配方”）。关键挑战在于新设计可能既包含与历史设计高度相似的结构（如加法器、乘法器），也可能包含完全新颖的方案（如新型处理器指令）。与现有工作相比，INVICTUS首次提出强化学习与搜索方法相结合的混合策略，并引入在线分布外检测器，可在广泛基准测试中生成综合配方。实验结果表明：所综合电路的面积延迟积（ADP）相比现有最优技术实现了最高30%的提升。此外，在与最优技术保持同等ADP的条件下，INVICTUS的运行时效率最高提升6.3倍。