Despite the increasing adoption of Field-Programmable Gate Arrays (FPGAs) in compute clouds, there remains a significant gap in programming tools and abstractions which can leverage network-connected, cloud-scale, multi-die FPGAs to generate accelerators with high frequency and throughput. To this end, we propose TAPA-CS, a task-parallel dataflow programming framework which automatically partitions and compiles a large design across a cluster of FPGAs with no additional user effort while achieving high frequency and throughput. TAPA-CS has three main contributions. First, it is an open-source framework which allows users to leverage virtually "unlimited" accelerator fabric, high-bandwidth memory (HBM), and on-chip memory, by abstracting away the underlying hardware. This reduces the user's programming burden to a logical one, enabling software developers and researchers with limited FPGA domain knowledge to deploy larger designs than possible earlier. Second, given as input a large design, TAPA-CS automatically partitions the design to map to multiple FPGAs, while ensuring congestion control, resource balancing, and overlapping of communication and computation. Third, TAPA-CS couples coarse-grained floorplanning with automated interconnect pipelining at the inter- and intra-FPGA levels to ensure high frequency. We have tested TAPA-CS on our multi-FPGA testbed where the FPGAs communicate through a high-speed 100Gbps Ethernet infrastructure. We have evaluated the performance and scalability of our tool on designs, including systolic-array based convolutional neural networks (CNNs), graph processing workloads such as page rank, stencil applications like the Dilate kernel, and K-nearest neighbors (KNN). TAPA-CS has the potential to accelerate development of increasingly complex and large designs on the low power and reconfigurable FPGAs.

翻译：尽管现场可编程门阵列（FPGA）在计算云中的应用日益广泛，但在编程工具和抽象机制方面仍存在显著空白，这些工具和抽象能够利用网络互联、云规模、多裸片FPGA来生成具有高频率和高吞吐量的加速器。为此，我们提出TAPA-CS，这是一个任务并行数据流编程框架，它能够自动将大型设计分区并编译到FPGA集群上，无需用户额外努力，同时实现高频率和高吞吐量。TAPA-CS有三项主要贡献。首先，它是一个开源框架，通过抽象底层硬件，允许用户利用几乎“无限”的加速器结构、高带宽内存（HBM）和片上内存。这降低了用户的编程负担至逻辑层面，使得缺乏FPGA领域知识的软件开发者和研究人员能够部署比以往更大规模的设计。其次，在输入大型设计时，TAPA-CS自动将设计分区以映射到多个FPGA上，同时确保拥塞控制、资源平衡以及通信与计算的重叠。第三，TAPA-CS在FPGA间和FPGA内层级上将粗粒度布局规划与自动互连流水线相结合，以确保高频率。我们已在多FPGA测试平台上测试了TAPA-CS，其中FPGA通过高速100Gbps以太网基础设施进行通信。我们在多种设计上评估了该工具的性能和可扩展性，包括基于脉动阵列的卷积神经网络（CNN）、图处理工作负载（如PageRank）、模板计算应用（如Dilate内核）以及K近邻算法（KNN）。TAPA-CS有潜力在低功耗可重构FPGA上加速日益复杂和大规模设计的开发。