As processor designs grow more complex, verification remains bottlenecked by slow software simulation and low-quality random test stimuli. Recent research has applied software fuzzers to hardware verification, but these rely on semantically blind random mutations that may generate shallow, low-quality stimuli unable to explore complex behaviors. These limitations result in slow coverage convergence and prohibitively high verification costs. In this paper, we present Lyra, a heterogeneous RISC-V verification framework that addresses both challenges by pairing hardware-accelerated verification with an ISA-aware generative model. Lyra executes the DUT and reference model concurrently on an FPGA SoC, enabling high-throughput differential checking and hardware-level coverage collection. Instead of creating verification stimuli randomly or through simple mutations, we train a domain-specialized generative model, LyraGen, with inherent semantic awareness to generate high-quality, semantically rich instruction sequences. Empirical results show Lyra achieves up to $1.27\times$ higher coverage and accelerates end-to-end verification by up to $107\times$ to $3343\times$ compared to state-of-the-art software fuzzers, while consistently demonstrating lower convergence difficulty.

翻译：随着处理器设计日益复杂，验证过程仍受限于缓慢的软件仿真和低质量的随机测试激励。近期研究尝试将软件模糊测试技术应用于硬件验证，但这些方法依赖于语义盲目的随机变异，可能产生浅层、低质量的激励，无法探索复杂行为。这些局限性导致覆盖率收敛缓慢，且验证成本高昂。本文提出Lyra——一种异构RISC-V验证框架，通过将硬件加速验证与指令集感知的生成式模型相结合，同时应对上述两大挑战。Lyra在FPGA SoC上并行执行被测设计与参考模型，实现了高吞吐量的差分验证和硬件级覆盖率收集。与随机生成或简单变异验证激励的传统方法不同，我们训练了具备固有语义感知能力的领域专用生成模型LyraGen，用以生成高质量、语义丰富的指令序列。实验结果表明，与最先进的软件模糊测试工具相比，Lyra的覆盖率最高提升$1.27\times$，端到端验证速度最高加速$107\times$至$3343\times$，同时持续展现出更低的收敛难度。