Hardware-firmware integration is becoming a productivity bottleneck due to the increasing complexity of accelerators, characterized by intricate memory hierarchies and firmware-intensive execution. While numerous verification techniques focus on early-stage, approximate modeling of such systems to speed up initial development, developers still rely heavily on FPGA emulation to integrate firmware with RTL/HLS hardware, resulting in significant delays in debug iterations and time-to-market. We present a fast, cycle-accurate co-verification framework that bridges production firmware and RTL/gate-level hardware. FIREBRIDGE enables firmware debugging, profiling, and verification in seconds using standard simulators such as VCS, Vivado Xsim, or Xcelium, by compiling the firmware for x86 and bridging it with simulated subsystems via randomized memory bridges. Our approach provides off-chip data movement profiling, memory congestion emulation, and register-level protocol testing, which are critical for modern accelerator verification. We demonstrate a speedup of up to 50x in debug iteration over the conventional FPGA-based flow for system integration between RTL/HLS and production firmware on various types of accelerators, such as systolic arrays and CGRAs, while ensuring functional equivalence. FIREBRIDGE accelerates system integration by supporting robust co-verification of hardware and firmware, and promotes a structured, parallel development workflow tailored for teams building heterogeneous computing platforms.

翻译：硬件-固件集成正成为生产力瓶颈，其根源在于加速器日益复杂——即复杂存储层次结构与固件密集型执行并存。尽管众多验证技术致力于通过早期阶段对这类系统进行近似建模以加速初始开发，开发者仍高度依赖FPGA仿真来实现固件与RTL/HLS硬件的集成，导致调试迭代周期显著延长，产品上市时间推迟。本文提出一种快速、周期精确的协同验证框架，能够桥接生产级固件与RTL/门级硬件。FIREBRIDGE通过将固件编译为x86架构指令，并借助随机化存储桥接器将其与仿真子系统对接，使得开发者可使用VCS、Vivado Xsim、Xcelium等标准仿真器在数秒内完成固件调试、性能剖析与验证。该方案提供片外数据搬运分析、存储拥塞模拟及寄存器级协议测试功能，这些对现代加速器验证至关重要。在脉动阵列与粗粒度可重构架构等多种加速器的系统集成场景中，相比传统基于FPGA的流程，我们的方法在确保功能等价性的前提下实现高达50倍的调试迭代速度提升。FIREBRIDGE通过支持硬件与固件的鲁棒协同验证加速系统集成，并为异构计算平台开发团队提供结构化的并行开发工作流支持。