Large language models (LLMs) have recently emerged as a promising approach for automating Verilog code generation; however, existing methods primarily emphasize syntactic correctness and often rely on commercial models or external verification tools, which introduces concerns regarding cost, data privacy, and limited guarantees of functional correctness. This work proposes a unified multi-agent framework for reasoning-oriented training data generation with integrated testbench-driven verification, enabling locally fine-tuned LLMs, SiliconMind-V1, to iteratively generate, test, and debug Register-Transfer Level (RTL) designs through test-time scaling. Experimental results on representative benchmarks (VerilogEval-v2, RTLLM-v2, and CVDP) demonstrate that the proposed approach outperforms the state-of-the-art QiMeng-CodeV-R1 in functional correctness while using fewer training resources.

翻译：大语言模型（LLMs）近期已成为自动化Verilog代码生成的一种有前景的方法；然而，现有方法主要强调语法正确性，且通常依赖商业模型或外部验证工具，这引发了关于成本、数据隐私以及功能正确性保障有限的担忧。本研究提出了一个统一的多智能体框架，用于生成面向推理的训练数据，并集成了测试平台驱动的验证，使得本地微调的大语言模型——硅智-V1——能够通过测试时扩展，迭代地生成、测试和调试寄存器传输级（RTL）设计。在代表性基准测试（VerilogEval-v2、RTLLM-v2和CVDP）上的实验结果表明，所提出的方法在使用更少训练资源的同时，在功能正确性方面优于当前最先进的启梦-CodeV-R1。